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    • 专利摘要:
    The invention relates to a method for manufacturing an electronic component (1) with multiple quantum islands, comprising the steps of: -providing a substrate (100) surmounted by a nanowire (111) of semiconductor material unintentionally doped, surmounted by at least two main control gates (112) so as to form respective qubits beneath these main control gates, said two main control gates being separated by a groove (114), the apex and the lateral faces of the two main control grids and the bottom of the groove being covered by a dielectric layer (106); deposition of a conductive material: in said groove (122); and on the top of the two main control grids; -planarization up to said dielectric layer at the top of the two main control gates (112), so as to obtain a conductive material element (122) self-aligned between said main control gates. Figure to be published with the abstract: Fig. 37
    公开号:FR3081155A1
    申请号:FR1854109
    申请日:2018-05-17
    公开日:2019-11-22
    发明作者:Louis HUTIN；Sylvain Barraud；Benoit Bertrand；Maud Vinet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT WITH MULTIPLE QUANTUM ISLANDS
    The invention relates to the field of spintronics, and in particular electronic components with multiple boxes, islands or quantum bits coupled together, as well as their manufacturing processes.
    Quantum electronics provide a foundation for performance improvements. By analogy with classical electronics, the quantum bit represents the basic element of computation for quantum electronics. In classical electronics, Boolean calculations are carried out using bits having one of two possible states. A quantum bit is a superposition of the eigenstates | 0> and | 1>.
    Quantum islands are the building blocks of quantum electronics. Quantum islands use semiconductor nanostructures to form potential wells to confine electrons or holes in three dimensions of space. The quantum information is then coded in purely quantum degrees of freedom: in this case the spin% of the electron. Quantum dots aim to isolate one or more charge carriers to define a qubit from their spin. By taking advantage of the quantum phenomena of superposition and entanglement, certain algorithms then make it possible to benefit from a polynomial or even exponential improvement of the computation time compared to their counterparts based on binary logic. According to one approach, electrons are confined by field effect under transistor gates, and the information is encoded in the spin of these electrons.
    To perform quantum logic operations, it is important to be able to:
    -manipulate the quantum state of qubits;
    -detect a change in the quantum states of qubits;
    - have qubits communicate with each other via an adjustable or modular quantum coupling.
    To communicate adjacent qubits with an adjustable coupling mechanism, it is known to adjust the Coulomb potential barrier between these adjacent qubits.
    According to certain designs, the control of a qubit is ensured by a primary grid positioned vertically from the qubit, the modulation of the potential barrier being ensured by a secondary grid positioned vertically from the space between two adjacent qubits.
    In order to ensure coupling between adjacent qubits, it may be important that these qubits are very close, which can impose a pitch of less than 100nm between the primary grids of these qubits.
    ICG011267-DD18662 EN Text Depot.docx
    The placement of a secondary grid between these primary grids can then prove problematic from an industrial point of view, the production of the secondary grids requiring a lithographic definition and an engraving precision that are difficult to achieve.
    The document "A two-qubit logic gate in silicon" by M. Veldhorst et al., Nature 526, 410-414, proposes to control the coupling between two qubits by having secondary grids between the primary grids of qubits. A dielectric layer is previously formed on the primary grids. The secondary grids extend laterally on the dielectric layer of these primary grids and are therefore partially superimposed on the adjacent primary grids. The dielectric layer provides electrical insulation between the control grids and these additional grids.
    This configuration makes it possible to implement a manufacturing process with reduced dimensional control constraints and with a certain tolerance for misalignment between the primary grids and the secondary grids.
    This configuration however generates a strong capacitive coupling between the primary and secondary grids which alters the operation of the high frequency component. The corresponding manufacturing process also still induces significant dimensional control constraints, and significant misalignment tolerance constraints.
    In one design, there may be a number of qubits aligned in series between two electrodes disposed at two ends of a nanowire, and used as carrier reservoirs. Such carrier reservoirs are distant from the middle qubits. The loading time of a median qubit by an elementary charge can be relatively long.
    The invention aims to solve one or more of these drawbacks. The invention thus relates to a method for manufacturing an electronic component with multiple quantum islands, comprising the steps of:
    -provision of a substrate surmounted by a nanowire of semiconductor material not intentionally doped, said nanowire being surmounted by at least two main control grids so as to form respective qubits in the nanowire under these main control grids, said two main control grids being separated by a groove, the top and the lateral faces of the two main control grids and the bottom of the groove being covered by a layer of dielectric;
    -deposit of a conductive material:
    -in said groove; and
    -on the top of the two main control grids;
    ICG011267-DD18662 EN Text Depot.docx
    -planarization to said dielectric layer at the top of the two main control grids, so as to obtain an element of self-aligned conductive material between said main control grids.
    The invention also relates to the following variants. Those skilled in the art will understand that each of the characteristics of the following variants can be combined independently with the above characteristics, without however constituting an intermediate generalization.
    According to a variant, said element of conductive material obtained is a secondary control grid.
    According to yet another variant, the method further comprises the connection of said secondary control grid to an interconnection line.
    According to another variant, said element made of conductive material comprises a part forming a contact by tunnel effect with a reservoir of carriers.
    According to yet another variant, said two main control grids provided are positioned between two other main control grids surmounting said nanowire so as to form two other respective qubits in the nanowire under these other main control grids.
    According to a variant, the manufacturing method comprises a step of forming a reservoir of carriers made of doped semiconductor material in contact with one end of said nanowire.
    According to another variant, the formation of the carrier reservoir comprises a step of growth by epitaxy of an element made of doped semiconductor material.
    According to yet another variant, the formation of the carrier reservoir comprises a step of ion implantation in one end of said nanowire.
    According to yet another variant, the step of forming a reservoir of carriers made of doped semiconductor material includes the formation of another reservoir of carriers made of doped semiconductor material in contact with another end of said nanowire.
    According to a variant, said main control grids supplied are offset from one another in a longitudinal direction of said nanowire.
    According to another variant, said main control grids provided are offset from one another by a pitch of between 60 and 120 nm.
    According to yet another variant, said planarization step includes the removal of the dielectric on the top of said main control grids.
    According to yet another variant, the method further comprises a partial removal of the conductive material between said main control grids, from
    ICG011267-DD18662 EN Depot Texte.docx so that the top of said formed conductive element is lower than the top of the main control grids.
    According to another variant, said conductive element formed is free of superposition on said main control grids.
    According to yet another variant, said supplied substrate is of the silicon on insulator type and comprises a buried insulating layer separating the nanowire from a part made of semiconductor material from the substrate, the method comprising a step of doping the semiconductor material under said insulating layer buried vertical to said groove.
    Other characteristics and advantages of the invention will emerge clearly from the description given below, by way of indication and in no way limitative, with reference to the appended drawings, in which:
    FIGS. 1 to 38 illustrate sectional and top views of a qubit component at different stages of an embodiment of a manufacturing process according to the invention;
    FIG. 39 to 82 illustrate sectional and top views of a qubit component at different stages of an embodiment of a manufacturing process according to another aspect of the invention;
    FIG. 83 is a diagram summarizing the steps implemented in the embodiment of the method illustrated in FIGS. 1 to 38;
    FIG. 84 is a diagram summarizing the steps implemented in the embodiment of the method illustrated in FIGS. 39 to 82;
    FIG. 85 illustrates a sectional view of a variant applied to the second aspect of the invention.
    Figures 1 to 38 illustrate sectional and top views of a qubit component at different stages of an embodiment of a manufacturing process according to the invention. FIG. 81 is a diagram summarizing the steps implemented in this method. The description of steps 901 to 908 is provided by way of illustration, but these steps are known per se to those skilled in the art and can be carried out differently.
    In Figures 1 and 2, step 901 is implemented. Here, a silicon on insulator type substrate is provided beforehand. A silicon layer 101 (for example unintentionally doped silicon) is thus placed on an insulating layer 100 of dielectric, typically made of S1O2. The invention can of course also be applied to a solid substrate or to a substrate having insulation with shallow insulation trenches.
    ICG011267-DD18662 EN Text Depot.docx
    In step 902, an etching of the silicon layer 101 is implemented to form a nanowire 111, as illustrated in FIGS. 3 and 4. The etching is for example of the mesa type.
    In step 903, a dielectric layer 102 is formed to encapsulate the nanowire 111, as illustrated in FIGS. 5 and 6. The dielectric layer 102 can for example be formed by thermal oxidation of the surface of the nanowire 111, or by deposition of 'a layer of dielectric.
    In step 904, a grid conductor layer 103 is formed full plate, as illustrated in FIGS. 7 and 8. The layer 103 can for example be made of highly doped polysilicon, of metal, or include a stack of polysilicon, of metal grid and dielectric.
    In step 905, a planarization step is advantageously implemented, as illustrated in FIGS. 9 and 10. Such a planarization can for example be implemented by mechanochemical polishing.
    In step 906, a step of forming a hard mask is implemented, as illustrated in FIGS. 11 and 12. The hard mask advantageously comprises here a superposition of a layer of nitride 104 and a layer of S1O2 105. The hard mask is dimensioned so as to be able to resist etching as defined in step 907.
    In step 907, an etching step is implemented so as to define the form of main grids 112, as illustrated in FIGS. 13 and 14. The main grids 112 are for example defined with an etching pitch of 90 nm, for example by a process of photolithography in deep ultraviolet by immersion. The etching is for example of the anisotropic type. Grooves are formed between the main grids 112 and typically have a width of between 40 and 60 nm with a layer 101 of silicon, or a width of between 50 and 100 nm with a layer 101 of GaAs.
    In step 908, a dielectric layer 106 is formed, typically a full plate, to encapsulate the main grids 112 and the nanowire 111, as illustrated in FIGS. 15 and 16. The dielectric layer 106 may for example include a layer of nitride of Silicon for a stop function during a subsequent engraving. The dielectric layer 106 may also include a lower layer of silicon oxide to promote the quality of the interface. The layer 106 is intended to form a separation between the main grids 112 and secondary grids detailed later. The layer 106 is formed so as to keep grooves 114 between successive main grids 112. The layer 106 typically has a thickness of between 5 and 15 nm.
    In step 909, according to a variant of the manufacturing process, a step of forming a mask 107 is defined defining openings 113
    ICG011267-DD18662 EN Depot Texte.docx for the formation of carrier reservoirs, as illustrated in Figures 17 and 18. Layer 106 is exposed on both sides of the ends of nanowire 111.
    In step 910, the dielectric layer 106 is removed at the bottom of the openings 113, as illustrated in FIGS. 19 and 20, in order to be able to carry out deposition by doped epitaxy in situ of carrier reservoirs according to a variant of the manufacturing process. This removal can for example be implemented by an appropriate anisotropic etching.
    In step 911, zones of carrier reservoirs 115 and 116 are formed on either side of the nanowire 111, as illustrated in FIGS. 21 and 22. The carrier reservoirs 115 and 116 are here formed by selective epitaxy of a doped semiconductor material, starting from the ends of the nanowire 111. The mask 107 is removed to reveal the residual part of the dielectric layer 106.
    According to another embodiment, it is also possible to envisage carrying out doping by ion implantation in the openings 113, at the end of step 909, in order to produce carrier reservoirs at the ends of the nanowire.
    111.
    In step 912, an encapsulation is carried out by depositing a layer of dielectric 108. Here, a mechanical-chemical polishing is carried out here, with stopping on the layer 106 above the main grids 112, or with stopping on the layer 104, as illustrated in FIGS. 23 and 24. The grooves between the main grids 112 are filled with the dielectric 108.
    Due to the previous planarization step, here it was easier to carry out a mechanochemical polishing with stop on the top of the main grids 112.
    In step 913, a step of forming a mask 109 is implemented defining an opening 117 for the formation of self-aligned secondary grids, as illustrated in FIGS. 25 and 26. The opening 117 forms an access to the main grids and at layer 108 up to the edge of carrier tanks 115 and 116. Layer 109 covers the vertical of carrier tanks 115 and 116. The opening 117 can be aligned with the longitudinal ends of the main grids 112. The opening 117 can however also define an offset with the ends of the main grids 112, so that these ends are covered by the layer 109.
    In step 914, a step of removing the dielectric 108 is implemented according to the pattern of the opening 117, as illustrated in FIGS. 27 and 28.
    In step 915, a step of forming a mask 121 defining openings 118 is implemented, as illustrated in FIGS. 29 and 30, for the formation of access contacts to the carrier tanks 115 and 116. The openings 118 are formed to discover the layer 108 vertically from the carrier tanks 115 and 116. Depending on the resistance of the layer
    ICG011267-DD18662 EN Depot Texte.docx dielectric 108, the formation of the openings 118 can be carried out simultaneously with step 913.
    In step 916, an anisotropic etching step of the layer 108 is implemented in the openings 118, so as to uncover part of the carrier reservoirs 115 and 116. As illustrated in FIGS. 31 and 32, the mask 121. Gorges 119 are cleared between the successive main grids 112.
    In step 917, a metallization step is implemented, so as to fill the openings 118 and the grooves 119. Then, a mechanopolishing step is implemented. A contact 125 is thus formed for the charge tank 115, a contact 126 for the charge tank 116 and secondary grids 122 (also designated by the term J-Gates in the literature, the letter J referring to the interaction d exchange between the qubits defined under the primary grids) between the main grids 112, as illustrated in FIGS. 33 and 34. The secondary grids 122 extend vertically to a coupling region of the nanowire 111. The main grids 112 are isolated from the secondary grids 122 by the dielectric layer 102. There are thus main grids 112 and secondary grids 122 extending across the nanowire 111. The secondary grids 122 can thus be formed with reduced capacitive coupling with the main grids 112, due to the absence of superposition of the secondary grids 122 on these main grids 112. Furthermore, such secondary grids 122 can t be formed without inducing an increase in the etching pitch of the main grids 112, the secondary grids 122 here being self-aligned with the main grids 112.
    In the example illustrated, the mechanopolishing step is carried out with a stop on the layer 103 of the main grids 112. It is also possible to envisage carrying out a mechanopolishing step with a stop on the layer 108 present on the main grids 112.
    In step 918, a step of partial removal of the metal from the secondary grids 122 is advantageously implemented, as illustrated in FIGS. 35 and 36. Such removal can for example be implemented by selective partial etching. Such selective partial etching is implemented either because of different materials for the secondary grids 122 and the layer 103, or because of the retention of the layer 108 above the main grids 112.
    By thus reducing the height of the secondary grids 122 relative to the main grids 112, it is possible to reduce the capacitive coupling between the secondary grids 122 and the main grids 112.
    In step 919, advantageous steps are implemented:
    ICG011267-DD18662 EN Text Depot.docx
    -forming of a dielectric layer 128 of passivation, typically full plate. The layer 128 is for example made of SiN;
    -forming of a dielectric encapsulation layer 127, typically full plate. The dielectric layer 127 is for example made of S1O2;
    -engraving and metallization, in order to form vias up to contact with the contacts 125 and 126 respectively, the main grids 112 and the secondary grids 122. In particular, vias 135 and 136 are formed until contact with the contacts 125 and 126 of carrier tanks 115 and 116, as illustrated in Figures 37 and 38;
    -forming interconnection lines 140 to 148 in contact with respective vias. Interconnection lines 145 and 146 are in contact with vias 135 and 13 respectively. Interconnection lines 143, 144, 147, and 148 are in contact with vias connected to secondary control grids 122. Interconnection lines 140 to 142 are in contact with vias connected to main control grids 112.
    The illustrated configuration shows that the various interconnection lines 140 to 148 make it possible to obtain individual contacts for each of the carrier tanks and each of the control grids, while being compatible with a very reduced etching pitch.
    The manufacturing method according to the invention thus makes it possible to obtain an electronic component 1 with multiple quantum islands including secondary control grids, with an optimal integration density, while limiting the amplitude of the parasitic capacities.
    In FIGS. 39 and 40, step 921 is implemented. Here, a silicon on insulator type substrate is provided beforehand. A layer of silicon 101 (for example unintentionally doped silicon) is thus placed on an insulating layer 100 of dielectric, typically made of SiO2. The invention can of course also be applied to a solid substrate or to a substrate having insulation with deep insulation trenches.
    In step 922, a step of forming a hard mask 151 is implemented, as illustrated in FIGS. 41 and 42. The hard mask 151 is here for example made of SiN. The hard mask 151 has a thickness adapted as a function of the desired width for carrier injection tracks detailed later.
    In step 923, the formation of a mask is implemented to define active zones and to facilitate elimination of the short-circuiting between the control grids, as illustrated in FIGS. 43 and 44. The mask formed is defined by photolithography. The mask formed comprises in particular bands 152, 153 and 154 parallel and oriented in a first direction. Bands 152, 153
    ICG011267-DD18662 EN Depot Texte.docx and 154 here have a width of 80 nm. The mask formed also has two bands 155 and 156 spaced from one another in the first direction (generally, for a number n of primary grids, there will be a number n-1 of secondary grids). The bands 155 and 156 are spaced apart, for example, by an engraving pitch of 90 nm. The bands 155 and 156 extend in a second direction, perpendicular to the bands 152 and 153. The bands 155 and 156 extend from the band 152 to the band 153. The bands 155 and 156 here have a width of typically between 20 and 30 nm.
    In step 924, the silicon layer 101 and the hard mask layer 151 are etched, according to the pattern of the mask defined in step 923. The layer 101 and the hard mask layer 151 are for example engraved according to an anisotropic engraving. After etching, the hard mask has strips 162, 163 and 164 parallel and oriented in the first direction, and corresponding to the patterns of the strips 152, 153 and 154 respectively. The mask formed also has two bands 165 and 166 spaced from one another in the first direction, and corresponding to the patterns of the bands 155 and 156. The bands 165 and 166 extend in the second direction, perpendicular to the bands 162 and 163. Strips 165 and 166 extend from strip 162 to strip 163. Strips 172 to 176 (detailed below) are formed in a residual layer of Silicon 171, in the same pattern as the strips 162 to 166 respectively. As illustrated in Figures 45 and 46, the mask defined in step 923 is removed.
    In step 925, an isotropic etching step is implemented, as illustrated in FIGS. 47 and 48. The isotropic etching step is carried out so as to keep part of the hard mask strips 162, 163 and 164 and so as to discover a part of bands of Silicon 172, 173 and 174. The bands of hard mask 165 and 166 are removed to discover the bands of Silicon 175 and 176. The engraving removed a width of 20 nm of hard mask from the edges . Such etching has made it possible to define protrusions 167 of hard mask facing bands 175 and 176. These protrusions 167 are pointed and make it possible to facilitate the injection of carriers into the qubits, at the end of the process of manufacturing. The etching step also makes it possible later to have a separation between the control grids.
    The strip 174 aims to allow the elimination of the short circuit between the upper gates. The strip 172 aims to form a nanowire in which the qubits are formed.
    In step 926, a dielectric layer 157 is formed to encapsulate the strips 172 to 176 of the silicon layer, as illustrated in FIGS. 49 and 50. The dielectric layer 157 can for example be formed by oxidation
    ICG011267-DD18662 EN Thermal depot Text.docx of the surface of the silicon strips, or by deposition of a dielectric layer.
    In step 927, a layer of gate conductor 129 is deposited. Layer 129 is here made of doped Polysilicon. A planarization step is then implemented with stopping on the hard mask, as illustrated in FIGS. 51 and 52. The planarization is for example implemented by mechanopolishing.
    In step 928, a grid hard mask layer 130 is formed, as illustrated in FIGS. 53 and 54. The hard mask 130 is for example formed from SiN. The layer 130 deposited may advantageously have a thickness of 10 nm maximum, to facilitate elimination of the short circuit and to obtain different types of control grids of the same thickness.
    In step 929, a step of forming a mask 131 by photolithography is implemented, as illustrated in FIGS. 55 and 56. The mask 131 defines the shape of the main grids. The etching step between the reservoirs of intermediate carriers being defined is for example 90 nm, for example by an immersion process by deep ultraviolet photolithography.
    In step 930, an etching step of the layer 130 is implemented, according to the pattern of the mask 131. The etching is interrupted on the polysicilicon layer 129. The etching is here of the anisotropic type. Grooves 132 are formed between bands of the pattern of the mask 131, as illustrated in FIGS. 57 and 58. Part of the hard mask layer 130 is kept vertical to the layer of Silicon 101. To facilitate etching stop in an intermediate part of the hard mask layer 130, a thin layer of another material is advantageously interposed between the hard mask 151 and the hard mask layer 130.
    In step 931, an etching is used to define the stacks of the main grids, according to the patterns of the mask 131. An anisotropic etching of the polysilicon layer, of the hard mask layer 130 and of the dielectric layer 157 is implemented so as to uncover the substrate 100 and the residual layer of Silicon 171. The residual layer of Silicon 17 is notably discovered at the level of the grooves 132 between the grid stacks 112.
    The mask is removed at the end of step 931, as illustrated in FIGS. 59 to 61. The configuration at the end of this step is illustrated according to two different cutting planes, shown in broken lines. FIG. 60 is a sectional view at the level of the grid stacks 112. In practice, lower stacks of main grids and upper stacks of main grids are provided on either side of the strip 162 of hard mask. The main upper grids aim here for example to write the
    ICG011267-DD18662 EN Text Depot.docx qubits. The lower main grids aim here for example to read the qubits.
    In step 932, a step of forming a dielectric layer 133 is implemented, as illustrated in FIGS. 62 and 63. The layer 133 is for example produced by a conformal deposition of S1O2. This dielectric layer 133 is subsequently intended to form electrical insulation between the main control grids and intermediate carrier conductors in the lower part, and intended to form electrical insulation between the main control grids and the secondary grids in the upper part. The dielectric layer 133 is notably formed in the bottom and on the lateral faces of the grooves 132. The thickness of the layer 133 defines the residual width in the grooves 132, and therefore the width of the intermediate carrier conductors formed subsequently.
    In step 933, a step of forming a layer of conductive material or of highly doped semiconductor material 134 is implemented to form Field Effect Grids. Band 173 contains impurities (by doping) which can generate free carriers. The interlayer conductors are intended to bring the carriers by field effect near the entrance to the quantum dots which define the qubits. A layer 134 conductive at low temperature makes it possible to make a field effect grid polarizable.
    Here, a full plate conformal deposition was made of the layer 134, as illustrated in FIGS. 64 and 65. The layer 134 is for example made of doped Polysilicon. The layer 134 formed in particular fills the grooves 132 between the stacks of the main control grids. Layer 134 partially extends vertically from a band coupling region 172.
    In step 934, a partial etching of the layer 134. is set up. The partial etching is for example an isotropic etching of the layer 134, with stopping on the layer 133. As illustrated in FIGS. 66 and 67, intermediate conductors carriers 120 of doped polysilicon are formed between the stacks of control grids 112. Spacers 139 of doped polysilicon are also formed on the side of the stacks of end control grids. The thickness of layer 134 is for example at least equal to half of the space between the main grids (of level 131).
    The etching stop on the layer 133 vertically of the strips 163 and 164 makes it possible to electrically isolate the intermediate conductors of carriers 120 from each other at their ends. One could also envisage a step of etching the ends of the intermediate carrier conductors 120, if the manufacturing process does not involve the formation of such strips 163 and 164.
    ICG011267-DD18662 EN Text Depot.docx
    In step 935, a step of removing the upper face of the layer 133 is implemented, as illustrated in FIGS. 68 and 69. The upper face of the grid stacks, of the residual silicon layer 171 and of the substrate 100 is then discovered. The layer 133 is kept between the intermediate conductors of carriers 120 and the grid stacks 112. The removal of the upper face of the layer 133 is for example implemented by isotropic etching.
    In step 936, a mask 180 is formed which has openings 181, as illustrated in FIGS. 70 and 71. The openings 181 reveal in particular the strips 163 and 163 and 164, as well as the ends of the strip 162 of hard mask . The mask 180 is for example formed by photolithography.
    In step 937, a removal of the hard mask appearing in the openings 181 is implemented, as illustrated in FIGS. 72 and 73. This thus proceeds to the removal of the strips 163 and 164 as well as to the removal of the longitudinal ends of the strip 162. Such removal is for example carried out by anisotropic etching. The residual silicon layer 171 is thus discovered at the level of the strips 173 and 174, and at the longitudinal ends of the strip 172.
    In step 938, self-aligned doping is implemented in the residual silicon layer 171, at the level of the opening 181, as illustrated in FIGS. 74 to 76. In this way carrier reservoirs 185 and 186 are formed at level of the longitudinal ends of the strip 172. Carrier reservoirs 183 and 184 are also formed in the strips 173 and 174 respectively. The mask 180 is removed at the end of the doping step.
    In step 939, a step of removing the hard mask layer 130 is implemented, as illustrated in FIGS. 77 and 78. In particular, layer 129 of the stacks 112 is discovered, as well as the carrier intermediate conductors 120.
    In step 940, a passivation layer 187 is formed, for example made of SiN. This layer 187 also serves as a contact etching stop, which makes it possible to etch the contacts on the Grids and on the carrier tanks at once (the selectivity of SiO2 with respect to SiN collects the step height).
    Passivation layer 187 is covered with an encapsulation layer
    188, for example in SiO2. Layer 188 is then subject to planarization, for example by a mechanopolishing step. We then obtain the configuration illustrated in FIG. 79.
    In step 941, a mask 189 is formed on the layer 188, for example by photolithography. The mask 189 provides openings either vertically to the carrier conductors 120 or vertically to the control grids 112. The layer 188 and the layer 187 are then etched according to the pattern of the layer
    189. We then have respective access to the various carrier conductors.
    ICG011267-DD18662 EN Text Depot.docx
    120 or to the control grids 112, or to the carrier tanks 183 to 186. The configuration illustrated in FIG. 80 is then obtained.
    In step 942, vias 190 are formed in a manner known per se through the layer 188, in the accesses previously provided. Each of the control grids 112, each of the carrier conductors 120 and each of the carrier reservoirs 183 to 186 thus has a respective electrical connection via.
    The carrier reservoir 183 can supply carriers by tunnel effect to the carrier conductors 120. These carrier conductors 120 extending up to the strip 172, they each make it possible to bring the carriers to respective qubits formed in this strip 172 Carriers can thus easily be brought even for qubits in a middle part of the band 172, and separated from the carrier tanks 185 and 186 by other qubits. Such a configuration is also obtained here without affecting the integration density, and by limiting the appearance of stray capacitances.
    We therefore obtain an electronic component 1 with multiple quantum islands with carrier reservoirs making it possible to inject carriers as close as possible to the qubits. This aspect of the invention proves to be particularly advantageous when at least three qubits are spaced apart from one another along a nanowire. Indeed, it is thus possible to easily inject carriers even for qubits distant from carrier reservoirs arranged at the ends of this nanowire.
    The method of manufacturing an electronic component 1 with multiple quantum islands described with reference to FIGS. 1 to 38 aims to form secondary grids interposed between the main control grids. However, it is also possible to envisage using such a method to form carrier conductors interposed between the main control grids. For this, we can consider forming an accumulation zone by field effect, attracting the carriers of the offset tank. A Grid creates by field effect an accumulation zone which attracts the carriers of the offset tank.
    One can for example consider forming an element 122 extending vertically from a carrier reservoir, and separated from this carrier reservoir by a thin layer of dielectric, for example a thickness of 5 nm or 10 nm of dielectric.
    It is thus possible to promote the injection of carriers for qubits distant from the carrier reservoirs 115 and 116, without affecting the integration density and without inducing excessive parasitic capacities. It is in particular possible to produce control grids 112 and elements 120 each having a length (dimension taken in the longitudinal direction of the strip 172) of between 30 and 50 nm, for example 40 nm.
    ICG011267-DD18662 EN Text Depot.docx
    It can be seen in FIG. 82 of this example that each of the carrier tanks and each of the control grids can have a dedicated contact.
    For the various aspects of the invention, using a substrate 100 of the silicon on insulator type, a rear grid is advantageously formed under the insulator layer of the substrate, vertically above a coupling region of the nanowire or of the semiconductor element used for the formation of qubits. FIG. 85 illustrates a configuration in which rear control grids 199 are formed vertically from the elements made of conductive material 120 and a region for coupling the strip of semiconductor material 172. The rear control grids are formed by doping in a layer of semiconductor material (typically of the unintentionally doped type) 110. The layer of semiconductor material 110 is placed under an insulating layer 100. The insulating layer 100 advantageously has a thickness of between 10 and 50 nm. A rear gate 199 is for example formed by doping the semiconductor under this insulating layer 100, with doping advantageously at least equal to 10 19 cm ′ 3 . The doping of the rear gates 199 can for example be carried out by ion implantation, for example before a step of depositing a semiconductor layer 101 on the insulating layer 100.
    The communication between two adjacent qubits being ensured by the coupling region between them, a rear control grid 199 makes it possible to adjust the quantum coupling between the confinement regions of the qubits. The rear grid 199 makes it possible in particular to adjust the degree of coupling between the two adjacent qubits by adjusting the tunnel barrier which separates them. Depending on the polarity applied to the rear gate 199, the tunnel barrier can be reduced (strong coupling) or increased (weak coupling, high confinement), with minimal coupling vis-à-vis the other tunnel junctions or the main control grids of the qubits.
    The rear control gate 199 is advantageously connected to a control circuit (not shown) configured to apply an electrical bias thereon.
    The variant illustrated in Figure 85 is shown here in its application to the second aspect of the invention. However, it can also be envisaged to apply it to the first aspect of the invention, by having rear control grids vertical to the secondary control grids.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    1. Method for manufacturing an electronic component (1) with multiple quantum islands, comprising the steps of:
    supply of a substrate (100) surmounted by a nanowire (111) made of unintentionally doped semiconductor material, said nanowire being surmounted by at least two main control grids (112) so as to form respective qubits in the nanowire ( 111) under these main control grids, said two main control grids being separated by a groove (114), the top and the lateral faces of the two main control grids and the bottom of the groove being covered by a dielectric layer ( 106);
    -deposit of a conductive material:
    -in said groove (122); and
    -on the top of the two main control grids;
    planarization up to said dielectric layer at the top of the two main control grids (112), so as to obtain an element made of conductive material (122) self-aligned between said main control grids.
    [2" id="c-fr-0002]
    2. Method of manufacturing an electronic component (1) according to claim
    1, in which said element made of conductive material is a secondary control grid (122).
    [3" id="c-fr-0003]
    3. Method of manufacturing an electronic component (1) according to claim
    2, further comprising the connection of said secondary control grid to an interconnection line.
    [4" id="c-fr-0004]
    4. A method of manufacturing an electronic component (1) according to claim 1, wherein said element of conductive material (120) formed comprises a part forming a contact by tunnel effect with a reservoir of carriers (173).
    [5" id="c-fr-0005]
    5. A method of manufacturing an electronic component (1) according to claim 4, wherein said two main control grids provided are positioned between two other main control grids surmounting said nanowire (111) so as to form two other respective qubits in the nanowire (111) under these other main control grids.
    [6" id="c-fr-0006]
    6. A method of manufacturing an electronic component according to any one of the preceding claims, comprising a step of forming a carrier reservoir (115, 116) of doped semiconductor material in contact with one end of said nanowire (111 ).
    ICG011267-DD18662 EN Text Depot.docx
    [7" id="c-fr-0007]
    7. The method of manufacturing an electronic component according to claim 6, wherein the formation of the carrier reservoir (115, 116) comprises a step of growth by epitaxy of an element made of doped semiconductor material.
    [8" id="c-fr-0008]
    8. A method of manufacturing an electronic component according to claim 6, wherein the formation of the carrier reservoir (115, 116) comprises a step of ion implantation in one end of said nanowire.
    [9" id="c-fr-0009]
    9. A method of manufacturing an electronic component according to any one of claims 6 to 8, wherein the step of forming a reservoir of carriers of doped semiconductor material includes the formation of another reservoir of carriers of doped semiconductor material in contact with another end of said nanowire (111).
    [10" id="c-fr-0010]
    10. A method of manufacturing an electronic component according to any preceding claim, wherein said main control grids (112) provided are offset from each other in a longitudinal direction of said nanowire.
    [11" id="c-fr-0011]
    11. The method of manufacturing an electronic component according to claim 10, wherein said main control grids (112) supplied are offset from one another by a pitch of between 60 and 120nm.
    [12" id="c-fr-0012]
    12. A method of manufacturing an electronic component according to any one of the preceding claims, wherein said planarization step includes removing the dielectric on the top of said main control grids (112).
    [13" id="c-fr-0013]
    13. A method of manufacturing an electronic component according to any one of the preceding claims, further comprising a partial withdrawal of the conductive material between said main control grids, so that the top of said formed conductive element is lower than the top main control grids (112).
    [14" id="c-fr-0014]
    14. A method of manufacturing an electronic component according to any one of the preceding claims, wherein said conductive element formed is free of superposition on said main control grids (112).
    [15" id="c-fr-0015]
    15. Method for manufacturing an electronic component according to any one of the preceding claims, in which the said supplied substrate (100) is
    ICG011267-DD18662 EN Text Depot.docx type Silicon on insulator and includes a buried insulator layer separating the nanowire (111) from a part made of semiconductor material from the substrate, the method comprising a step of doping the semiconductor material under said insulating layer buried vertical to said groove.
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    同族专利:
    公开号 | 公开日
    FR3081155B1|2021-10-22|
    US20190371908A1|2019-12-05|
    US11088259B2|2021-08-10|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20150279981A1|2013-03-14|2015-10-01|Wisconsin Alumni Research Foundation|Direct tunnel barrier control gates in a two-dimensional electronic system|
    WO2014146162A1|2013-03-20|2014-09-25|Newsouth Innovations Pry Limited|Quantum computing with acceptor-based qubits|
    WO2015184484A1|2014-06-06|2015-12-10|Newsouth Innovations Pty Limited|Advanced processing apparatus|
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    WO2017213637A1|2016-06-08|2017-12-14|Intel Corporation|Quantum dot devices with patterned gates|
    US8829492B2|2010-11-05|2014-09-09|Chungbuk National University Industry-Academic Cooperation Foundation|Multiple quantum dot device and a production method for the device|
    WO2017210790A1|2016-06-08|2017-12-14|Socpra Sciences Et Génie S.E.C.|Electronic circuit for control or coupling of single charges or spins and methods therefor|
    FR3081155B1|2018-05-17|2021-10-22|Commissariat Energie Atomique|MANUFACTURING PROCESS OF AN ELECTRONIC COMPONENT WITH MULTIPLE QUANTUM ISLANDS|FR3081155B1|2018-05-17|2021-10-22|Commissariat Energie Atomique|MANUFACTURING PROCESS OF AN ELECTRONIC COMPONENT WITH MULTIPLE QUANTUM ISLANDS|
    US11107966B2|2019-11-11|2021-08-31|International Business Machines Corporation|Two-sided Majorana fermion quantum computing devices fabricated with ion implant methods|
    US11107965B2|2019-11-11|2021-08-31|International Business Machines Corporation|Majorana fermion quantum computing devices fabricated with ion implant methods|
    法律状态:
    2019-05-31| PLFP| Fee payment|Year of fee payment: 2 |
    2019-11-22| PLSC| Publication of the preliminary search report|Effective date: 20191122 |
    2020-05-30| PLFP| Fee payment|Year of fee payment: 3 |
    2021-05-31| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1854109|2018-05-17|
    FR1854109A|FR3081155B1|2018-05-17|2018-05-17|MANUFACTURING PROCESS OF AN ELECTRONIC COMPONENT WITH MULTIPLE QUANTUM ISLANDS|FR1854109A| FR3081155B1|2018-05-17|2018-05-17|MANUFACTURING PROCESS OF AN ELECTRONIC COMPONENT WITH MULTIPLE QUANTUM ISLANDS|
    US16/413,652| US11088259B2|2018-05-17|2019-05-16|Method of manufacturing an electronic component including multiple quantum dots|
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